# Enabling / disabling ROMs

Summary

Enabling / disabling ROMs |
Enabling / disabling ROMs | This 4 functions enable / disable lower or upper ROMs.
cpct_enableUpperROM | Enables Upper ROM [0xC000 - 0xFFFF]
cpct_enableLowerROM | Enables Lower ROM [0x0000 - 0x3FFF]
cpct_disableUpperROM | Disables upper ROM [0xC000 - 0xFFFF]
cpct_disableLowerROM | Disables Lower ROM [0x0000 - 0x3FFF]
Lower ROM | [ 0x0000 - 0x3FFF ]
Upper ROM | [ 0xC000 - 0xFFFF ]

### Enabling / disabling ROMs

This 4 functions enable / disable lower or upper ROMs.

#### C Definitions

void cpct_enableUpperROM ()

void cpct_enableLowerROM ()

void cpct_disableUpperROM ()

void cpct_enableUpperROM ()

#### Assembly calls

>     call cpct_enableUpperROM_asm
>     call cpct_enableLowerROM_asm
>     call cpct_disableUpperROM_asm
>     call cpct_enableUpperROM_asm

#### Known limitations

- If the execution of your program is going through some of these 2 ROM spaces and you enable ROM, CPU will be unable to get machine code of your program, as it will start reading from ROM instead of RAM (where your program is placed). This will result in unexpected behaviour.
- Enabling Lower ROM re-enables Firmware JMP in interrupt mode 1, as it re-establishes the values at memory location 0x0038. If you have disabled the firmware by putting FB:C9 (EI:RET) at 0x0038 (as cpct_disableFirmware does) you may experience undesired behaviour when next interrupts come. The most typical is a return to MODE 1, as firmware may be unaware of your currently selected MODE and will try to re-establish its own MODE. Take it into account and disable interrupts if you need.
- This function will not work from ROM, as it uses self-modifying code.

#### Details

These 4 functions enable / disable lower or upper ROMs. By default, CPCtelera sets both ROMS as disabled at the first event of video mode change. Enabling one of them means changing the way the CPU gets information from memory: on the places where ROM is enabled, CPU gets values from ROM whenever it tries to read from memory.

If ROM is disabled, these memory reads get values from RAM. ROMs are mapped in this address space:

CPU Requests to write to memory are always mapped to RAM, so there is no need to worry about that. Also, Gate Array always gets video memory values from RAM (it never reads from ROM), so enabling Upper ROM does not have any impact on the screen.

#### Destroyed Register values

AF, BC, HL

#### Required memory

33 bytes

#### Time Measures

>     Case  | microSecs(us) | CPU Cycles
>     -----------------------------------
>     Best  |      23       |     92
>     -----------------------------------
>     Worst |      26       |    104
>     -----------------------------------

### cpct_enableUpperROM

Enables Upper ROM [0xC000 - 0xFFFF]

### cpct_enableLowerROM

Enables Lower ROM [0x0000 - 0x3FFF]

### cpct_disableUpperROM

Disables upper ROM [0xC000 - 0xFFFF]

### cpct_disableLowerROM

Disables Lower ROM [0x0000 - 0x3FFF]

### Lower ROM

[ 0x0000 - 0x3FFF ]

### Upper ROM

[ 0xC000 - 0xFFFF ]

Enables Upper ROM [0xC000 - 0xFFFF]
Enables Lower ROM [0x0000 - 0x3FFF]
Disables upper ROM [0xC000 - 0xFFFF]
Disables Amstrad CPC firmware, preventing it from being executed at every CPU interrupt.
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